__4.
Practicable circuits__

__ __

The
simulated pulse-width-modulated circuit runs with a 200kHz clock driving a four
stage divide-by-12 counter. The Philips 74HCT4046 includes a VCO that is
guaranteed to run at least 11MHz with 2.5V at the control input.

A nine-stage
divider would allow this clock to run at a nominal 6.14MHz. The $1.70 Xilinix
XCR3032XL will accommodate a counter of this length, running at this frequency,
while drawing about 1mA.

The faster
clock could be exploited to set up a low distortion sine-wave source for
lightly loaded tank circuits, by using one of Don Lancaster’s “magic sine wave”
binary sequences to match the voltage at the driven end of L3 to the repeating
half-sine wave at the centre tap.

Granting
the relatively coarse clock, this would presumably approximate the sine wave
with three progressively wider pulses along the rising edge, an even wider
pulse around the peak and three progressively narrower pulses along the falling
edge.

This should
reduce the AC current through the inductor to quite low levels, and very nearly
eliminate the low order harmonic content of the output waveform.

As the load
on the tank circuit increases, the inductor has to deliver a half-sine current,
in-phase with the voltage at the centre-tap, to provide the current being
absorbed by the resistive component of the load.

In the
simulated circuit, this can be effected – to some extent - by moving the drive
wave-form to the left as the load increases. We’d have 32 discrete steps
available if we did it digitally.

In fact,
the desired voltage waveform across the inductor is the integral of desired
current waveform through the inductor, which is just the cosine wave; the
amplitude of this cosine wave has to be adjusted to match the load on the tank
circuit. With the 3.5 pulse approximation to the sine wave we’d initially add a
minimum width positive pulse at the 0° end of the sequence, and shave one clock
pulse width off the last pulse in the sequence (at around 163°), then progressively shift more of the
“on” time from the right hand end of the sequence to the left. There wouldn’t
be that many pulses to play with, so we’d be unlikely to be able to contrive
even 32 discrete steps.

__5.
Practical circuit – Analog phase-sensitive detection and frequency control__

__ __

The pulse width modulated circuit needs a
phase-sensitive detector to adjust the clock frequency to the resonant
frequency of the tank circuit.

In fact what we want to do is to adjust the
clock frequency such that the switching transistors M1 and M2 switch at the
zero-crossing point where the voltage at free ends of L2 and L1 are
respectively zero. This doesn’t necessarily coincide with the resonant
frequency of the tank circuit.

The simplest way to do this would be to
integrate the 0° to 90° voltage at the centre-tap and compare it with the
integral of the 90° to 180° voltage, which could be done with a 4066 switch and
a differential amplifier wired up as an integrator. The output of the
integrator would control the voltage applied to the voltage-controlled
oscillator (VCO) in the 4046 to keep these two integrals as nearly equal as
possible

This has the disadvantage that the peak voltage
at the centre tap starts peaking earlier than 90° as the load on the tank
circuit increases, which would duplicate the effect of the clock running too
slowly. We could reduce the effect of this particular distortion by making the
phase-sensitive detector into a box-car integrator and integrate only from 0°
to 45° and from 135° to 180°.

We could further reduce the effect by adding a
second control loop using a second phase-sensitive detector looking
specifically at the position of the peak by integrating from 45° to 90° and
comparing this sum with the integral from 90° to 135°. This detector would be
more sensitive to the position of the peak than the position of the
zero-crossing point, and could be used to centre the peak by adjusting the
phase of the drive waveform at L3 with respect to the switching points of M1
and M2.

The first control loop – to force switching at
the zero-crossing points of the tank circuit – would have to be slow enough to
avoid exciting the 5kHz resonance of L3 with the tank circuit. Because the VCO
is a phase integrator, the integrator in the phase sensitive detector would
have to have the usual phase advance resistor to prevent the loop from
oscillating.

The second control loop would have to be even
slower, which ought not to be a problem.

__6. Practical circuit – digital control.__

__ __

It is a truism that most control tasks in low-frequency electronics can be handled by a single-chip microprocessor. This appears to be true here.

A single chip microprocessor with a roughly
20MHz clock, a built-in A/D converter and a 16-bit counter-timer or two – the
Microchip 18F6620 looks as if it might do the work – should be able to do the
whole job.

The disadvantages are that the output period
would have to be adjusted in discrete steps of
100nsec, (0.16%) and any attempt to use the “magic sinewave” technique
to minimize higher harmonics would require a lot of program to adjust the pulse
widths for every change in frequency. The A/D converter would be used to sample
the voltage at the centre tap at the 22.5°, 67.5°, 112.5° and 157.5° points and
the processor would adjust the drive frequency and the drive phase accordingly.